1. Field of the Invention
The present invention relates to a TFT (Thin Film Transistor) array having a plurality of TFTs arranged in the form of a matrix, and each having a pixel electrode and made by stacking a gate electrode, a semiconductor layer, a source electrode, a drain electrode, and the like, on a transparent insulation substrate.
2. Description of the Related Art
Conventional TFTs as switching elements are disclosed in Published Examined Japanese Utility Model No. 44-5572 (U.S. Ser. No. 132,095), Published Examined Japanese Patent Application No. 41-8172 (U.S. Ser. No. 344,921), and P.K. Weimer, "The TFT--A New Thin-Film Transistor", PROCEEDlNGS OF THE IRE, June, 1962. Liquid crystal display panels using such TFTs are disclosed in "A 6.times.6 Inch 20 lines-Per-Inch Liquid Crystal Display Panel", IEEE Transactions on Electron Device, vol. ED-20, No. 11, Nov. 1973 and U.S. Pat. No. 3,840,695.
On the other hand, U.S. Pat. Nos. 3,765,747 and 3,862,360, and Published Unexamined Japanese Patent Application Nos. 55-32026, 57-20778, and 58-21784 disclose a technique wherein a MOS transistor is formed on a monocrystalline semiconductor substrate, and the resultant structure is used as one of the substrates of a liquid crystal display panel. However, if liquid crystal panels are constituted by these semiconductor substrates, only reflection type displays can be obtained. In addition, the manufacturing process of such panels are as complex as that of LSIs. Moreover, it Is difficult to obtain a large display panel.
The above-described active matrix liquid crystal panels, therefore, has TFTs used as switching elements. The structures of these TFTs can be classifield into a coplanar type, an inverted coplanar type, a staggered type, and an inverted staggered type, as disclosed in the article by P.K. Weimer. Of these types, the inverted staggered type TFT can be formed by stacking a plurality of thin films successively in a vacuum. For this reason, the number of manufacturing steps is substantially decreased. As a result, the characteristics of a product are stabilized, and the rate of occurrence of defective transistors is decreased.
FIGS. 1 and 2 show structures of the above-described inverted staggered type TFT and a TFT array obtained by arranging a plurality of such inverted staggered type TFTs on an insulating substrate. Referring to FIGS. 1 and 2, a plurality of TFTs 1 are arranged on a transparent insulating substrate 2 in the form of a matrix. Gate electrodes 3 of TFTs 1 are connected by a gate line 4 extending in the row direction. Drain electrodes 5 of TFTs 1 are connected by a drain line 6 extending in the column direction. A source electrode 7 of each TFT 1 is connected to a transparent electrode 8 independently formed in an area surrounded by the gate and drain lines 4 and 6 (an electrode, to which a data signal is supplied, will be referred to as a drain electrode hereinafter). More specifically, as shown in FIG. 2, the gate electrode 3 consisting of Cr or the like is formed on the transparent glass substrate 2, and a gate insulating film 9 consisting of silicon oxide or silicon nitride is formed on the upper surface of the glass substrate 2 including the upper surface of the gate electrode 3. A semiconductor film 10 consisting of amorphous silicon is stacked on the gate insulating film 9 above the gate electrode 3. Drain and source electrodes 5 and 7 are formed on the semiconductor film 10. They are separated from each other by a predetermined distance, forming channel portion 11. Drain and source electrodes 5 and 7 respectively have contact layers 5a and 7a, and metal layers 5b and 7b, and are electrically connected to the semiconductor 10. The source electrode 7 is connected to the transparent electrode 8 consisting of Indium-Tin-Oxide (to be referred to as an ITO hereinafter).
In the TFT used for the above-described TFT array, since part of the drain electrode 5, the drain line 6, and the transparent electrode 8 are formed on the gate insulating film 9, both the electrodes tend to be short-circuited, and hence the rate of occurrence of defects becomes high. Especially in the TFT array using this TFT, since the transparent electrode 8 is formed in a region surrounded by the gate and drain lines 4 and 6, short-circuiting tends to occur between the transparent electrode 8 and the drain line 6.
In order to prevent such short-circuiting, predetermined distance L determined by process and alignment precision in formation of the transparent electrode 8 and the drain line 6 is formed therebetween. Distance L is usually as along as 20 .mu.m, or more. Although the long distance L can prevent the above-described short-circuiting, the area of the transparent electrode 8 is reduced. That is, the problem of reduction in effective display area is posed. For example, the opening ratio, i.e., the ratio of the area of the transparent electrode 8 to an area for arranging one TFT and one transparent electrode on the glass substrate 2 becomes as small as about 50% even if distance L is reduced to a minimum of 20 .mu.m.